Synopsys, Ansys and Keysight Accelerate 5G/6G SoC Designs with New mmWave Reference Flow for TSMC Process Technology 2022-10-27 16:47:00 EDA
Cadence's New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies 2022-10-27 10:00:00 EDA
GUC Unveils GLink 2.3LL, The World's Most Powerful D2D Interconnect IP Using 2.5D Technology 2022-10-26 12:33:00 IP
Worldwide Silicon Wafer Shipments Set a New Record in Q3 2022, SEMI Reports 2022-10-26 08:58:00 Commentary / Analysis
More than 50 members join SOAFEE to enable the software-defined vehicle of the future 2022-10-26 08:38:00 Other
Cadence Digital and Custom/Analog Design Flows Achieve Certification for TSMC's Latest N4P and N3E Processes 2022-10-26 07:55:00 EDA
Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0 2022-10-25 14:49:00 Verification IP
Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum 2022-10-25 08:54:00 Other
Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs 2022-10-25 08:07:00 IP
Cadence Joins Intel Foundry Services USMAG Alliance to Accelerate Chip Design Development 2022-10-25 08:04:00 EDA
Synopsys Advances Designs on TSMC N3E Process with Production-Proven EDA Flows and Broadest IP Portfolio for AI, Mobile and HPC Applications 2022-10-24 16:13:00 IP