Standard cell libraries IP

The Standard Cell libraries deliver thousands of highly optimized cells with each one being optimized for power, area, speed, routing, and yield.
These libraries may be extended with Power Management Kits, taking power reduction to the next level, and ECO Kits to enable late-stage design modifications.

Contains >300 cells, various Vt and channel length options
Robust power supply rails on M2, optimized M1 pin access with at least two on-track M2 access points
DFM and variability optimized layouts and variation aware placement attributes for automated place&route
Enabled for reliable ULV operation down to 0.4 V in combination with adaptive forward body bias

Basic Cells: A full suite of fundamental logic gates and flip-flops.
Optimal Cells: High-performance variants of basic cells, optimized for power, area, and speed, including high-speed flip-flops, advanced multiplexers, clock gated cells, clock buffers, arithmetic cells and custom-designed cells for critical paths.

standard cell libraries IP