Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P

Overview

The low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance SoC designs. A nominal operating voltage of 0.45 V. Silvaco’s N3P Standard Cell Libraries enable designers the greatest flexibility in managing the power efficiency for any design.

Low Voltage SoC Design Challenges

Low Voltage System-on-Chip (SoC) design holds paramount significance in the realm of electronics and semiconductor engineering. The importance of low voltage design lies in its ability to enhance energy efficiency, reduce power consumption, and extend the battery life of electronic devices. As technology advances, the demand for smaller, more portable devices with longer battery life has become increasingly critical. Low voltage SoC design addresses this need by optimizing the power supply voltage to the lowest feasible level without compromising the performance of the integrated circuits. This not only benefits the environment by reducing energy consumption but also caters to the growing market for energy- efficient and sustainable electronic products.

Silvaco Standard Cell Libraries for Low Voltage Operation

The challenges of designing a robust Standard Cell Library that can operate at a low voltage is extremely challenging. Ensuring stable and reliable operation, high yields, and robust operating temperature are all essential elements to ensuring your design success. Relying on more than 30 years of low-voltage expertise, Silvaco continues to push the boundaries previously thought unachievable.

Corners

  • Nominal Voltage
  • ffgnp_0p44v_125c_cbest_CCbest_T
  • fgnp_0p44v_m40c_cbest_CCbest_T
  • ssgnp_0p36v_125c_cworst_CCworst_T
  • ssgnp_0p36v_m40c_cworst_CCworst_T
  • tt_0p40v_85c_typical
  • tt_0p40v_25c_typical

Key Features

  • Operating voltage 0.45 V +/-10 %
  • Library augmented with over 150 cells optimized for performance at 0.45 V (e.g., 3 / 4 input devices)
  • Track height: 7.5T
  • Poly pitch 48nm, cell height 169.0nm
  • Operating temperature: -40°C to 125°C
  • Optimized for performance and yield with Silvaco tools

Deliverables

  • Views
  • Verilog gate-level
  • Liberty Files (timing and power)
  • GDSII
  • LVS Netlist
  • Datasheet

Technical Specifications

Foundry, Node
TSMC, 3nm
Maturity
Pre-silicon
Availability
Now
GLOBALFOUNDRIES
Pre-Silicon: 55nm
×
Semiconductor IP