Emmc 5.1 IP

The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.

The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications.
This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.

The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
eMMC 5.1 is backward compatible to the previous versions.

eMMC 5.1 Nex Bus Driver is a production-ready software stack for eMMC 5.1 Host Controller IP that is used to connect eMMC devices.
The eMMC 5.1 stacks can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.

The eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50 specification. It is backward compliant with eMMC4.51 and earlier versions of the specifications.
This allows the designers of the SoC to easily support the EMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 hosts.

The eMMC 5.1 Device Controller IP is compliant with the latest eMMC specification. The controller provides a bandwidth of up to 3.2 Gb/s (400MB/s) in HS400 DDR mode running with a 200 MHz clock.
A NAND Flash controller can be connected to the eMMC controller. In such an implementation, the controller’s AHB interface provides a channel for data transfers between the eMMC device controller and a NAND flash controller (also available from Arasan).

High speed modes
200 MB/s Read and Write operation. HS400 Dual Data Rate Read and Write interface
General eMMC Functionality
48-bit input command format and R1, R1b, R2 response formats

Compliant to the eMMC Electrical Standard 5.1A
Supports Backwards Compatible, High Speed SDR, High Speed DDR, HS200 and HS400 transfer modes
Host transfer rate of up to 400 MByte/s in HS400 mode

eMMC 5.1 IP