eMMC Device Controller

Overview

eMMC 5.1 IP fully compliant to JEDEC JESD-84-B51, supporting full backwards compatibility, high speed SDR, high speed DDR, HS200 and HS400 transfer modes. host transfer rate of up to 400 MByte/s in HS400 mode, supporting 1, 4 and 8 bit bus width.

Key Features

  • Compliant to the eMMC Electrical Standard 5.1A
  • Supports Backwards Compatible, High Speed SDR, High Speed DDR, HS200 and HS400 transfer modes
  • Host transfer rate of up to 400 MByte/s in HS400 mode
  • Supports 1, 4 and 8 bit bus width
  • Supports 3.3V and 1.8V signaling level

Benefits

  • compatible with Synopsys VIP incl. test-bench extensions
  • On request full software support and drivers can be made available
  • Silicon proven and in mass production
  • Proven Testmetrix compliance
  • Wide host system compatibility
  • FPGA ready
  • Performance optimized memory interface (128-bit)
  • Optional complementary security software or hardware IP available also to support eMMC security extension

Block Diagram

eMMC Device Controller Block Diagram

Applications

  • eMMC Devices
  • eMMC memories
  • eMMC Flash storage products

Deliverables

  • Specification & data book
  • Verilog code (encrypted)
  • Verilog code (non encrypted on request available)
  • GDS II data on request (GF40)
  • Synthesis scripts (FPGA & ASIC)
  • STA constraints (GF40)
  • DFT ready
  • RAL register description

Technical Specifications

Maturity
Silicon proven in mass production
Availability
Now
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Semiconductor IP