IP Catalog > EMMC 5.0

eMMC 5.0 IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (21)
Compare 21 IP from 9 vendors (1 - 10)
  • SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
    • Memory Card / Form Factors:
    • IP Details:
    Block Diagram -- SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
  • Simulation VIP for eMMC
    • High speed modes
    • 200 MB/s Read and Write operation. HS400 Dual Data Rate Read and Write interface
    • General eMMC Functionality
    • 48-bit input command format and R1, R1b, R2 response formats
    Block Diagram -- Simulation VIP for eMMC
  • eMMC LDPC Encoder/Decoder
    • Supports data rates from 50 MB/s to 9.0 GB/s.
    • Enables custom LDPC core development for specific requirements.
    • Wide range of codeword sizes.
    • Maximum supported parity.
    Block Diagram -- eMMC LDPC Encoder/Decoder
  • ONFI 5.0 PHY IP
    • Compliant with ONFI 5.0 specification
    • Supports NV-DDR2 mode
    • Supports NV-DDR3, NV-LPDDR4, with a maximum rate of 2400MT/s
    • Supports PHY Independent TX/RX Training mode
    Block Diagram -- ONFI 5.0 PHY IP
  • SD 5.1 / eMMC 5.1 Host Controller IP
    • SD IP Features :
    • Support SD system specification version 5.1
    • Support Application Performance Class 1.
    • Backward compatible to SD2.0 host
    Block Diagram -- SD 5.1 / eMMC 5.1 Host Controller IP
  • SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
    • Fully compliant core with proven silicon
    • Premier direct support from Arasan IP core designers
    • Easy-to-use industry standard test environment
  • eMMC 5.1 Host Controller
    • Compliant with eMMC Specification Version 5.0
    • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
    Block Diagram -- eMMC 5.1 Host Controller
  • eMMC 5.1 Device Controller
    • Compliant with eMMC 5.1 specification
    • Peak bandwidth of 3.2 Gbps or 400 MB/s
    • Additional Data Strobe signal for HS400 mode
  • IO 3.3V eMMC in GF (22nm)
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
×
Semiconductor IP