eMMC 5.0 IP
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16
IP
from 4 vendors
(1
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10)
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SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
- Memory Card / Form Factors:
- IP Details:
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SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
- Fully compliant core with proven silicon
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
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eMMC 5.1 Host Controller
- Compliant with eMMC Specification Version 5.0
- Supports one of the following System/Host Interfaces: AHB, AXI or OCP
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ONFI 5.0 PHY IP
- Compliant with ONFI 5.0 specification
- Supports NV-DDR2 mode
- Supports NV-DDR3, NV-LPDDR4, with a maximum rate of 2400MT/s
- Supports PHY Independent TX/RX Training mode
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SD 5.1 / eMMC 5.1 Host Controller IP
- SD IP Features :
- Support SD system specification version 5.1
- Support Application Performance Class 1.
- Backward compatible to SD2.0 host
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eMMC 5.1 Device Controller
- Compliant with eMMC 5.1 specification
- Peak bandwidth of 3.2 Gbps or 400 MB/s
- Additional Data Strobe signal for HS400 mode
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IO 3.3V eMMC in GF (22nm)
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
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SD 4.1 SDIO 4.1 Host Controller IP
- SD4.0
- SDIO4.0
- eMMC5.0
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TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
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TSMC 3nm (N3E) 1.8V SD/eMMC IO
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified