Xylon IP
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Video Design Framework for Multi-camera Vision Applications
- Complete video design framework for embedded multi-camera vision applications
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Lossless MJPEG Decoder
- Plug-and-Play IP core with Xilinx implementation tools (Vivado)
- Free reference designs available for AMD-Xilinx ZCU102 on request
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Lossless MJPEG Encoder
- Plug-and-Play IP core with Xilinx implementation tools (Vivado)
- Free reference designs available for AMD-Xilinx ZCU102 on request
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HDR ISP framework for multi-camera applications
- Complete HDR ISP video processing framework for multi-channel vision and AI systems
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Motion JPEG Encoder
- Supports Xilinx® Zynq®-7000 AP SoC and 7 series FPGA families
- Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
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Driver Drowsiness Detector
- Optimized for Xilinx® Zynq®-7000 AP SoC
- Driver drowsiness detector based on the video input from the optical camera
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Multi-Channel MJPEG Decoder
- Supports Xilinx® Zynq®-7000 AP SoC and 7 series FPGA families
- Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
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UHD Image Signal Processing (ISP) Pipeline
- The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx ACAP, MPSoC, SoC and FPGA devices.
- It enables parallel processing of multiple Ultra HD video inputs in different programmable devices, ranging from the small Xilinx Artix®-7 FPGAs to the latest Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) devices.
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Programmable Clock Generator
- Easily solve different clocking schemes in Xilinx device and adopt clocking during the SoC operation
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SD Card Host Controller
- Meets SD Host Controller Standard Specification Version 2.00
- Supports single and multiple SD cards
- Compliant to CoreConnect(TM) PLB bus
- Parametrizable VHDL design