The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx ACAP, MPSoC, SoC and FPGA devices. It enables parallel processing of multiple Ultra HD video inputs in different programmable devices, ranging from the small Xilinx Artix®-7 FPGAs to the latest Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) devices. In comparison to simple instantiation of multiple ISP pipelines within a single programmable device, the latest IP cores’ improvements allow for tremendous savings of up to 50 % of valuable programmable logic.
The logiISP-UHD IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. The IP core can be used with processor-based control algorithms for Auto White Balancing (AWB) and Auto Exposure (AE), which use video analytics data collected by the ISP pipeline. Xylon offers licensable AWB&AE libraries for the logiISP-UHD IP core.
The logiISP-UHD IP core supports spatial resolutions up to 7680x7680, including 4K2Kp60 (3840x2160@60fps) resolution, and accepts Raw Bayer, RGB and YCbCr video input formats featuring different pixel color depths (8/10/12-bit per pixel). It outputs RGB or YCbCr-formatted processed video and easily adapts to changing image sensor interfaces.
