XAUI IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Compare 228 IP from 28 vendors (1 - 10)
  • XAUI PHY
    • ? 3.125-Gbps transmissions rate
    • ? Supports x4 configuration
    • ? Integrated regulator to support either 3.3-V or 2.5-V I/O power supply
    • ? Excellent performance margin and receiver sensitivity
  • XAUI XGMII Extender
    • Fully compliant with IEEE 802.3ae Clause 47
    • Supports 802.3ae Clause 45 MDIO interface
    • Tolerance oflane skew up to 16ns (50 UI)
    • IEEE 802.3ae PICs compliance matrix
  • Ethernet XAUI PCS
    • 64-bit demuxed XGMII works with Cadence XGM 10G Ethernet MAC
    • Standard 10-bit data path
    • Built-in Idle conversion
    • Optional MDIO interface for PHY management
  • 4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)
    • 4 channel SERDES capable of operating at 1.25, 2.5-3.125 and 5-6.25Gbps.
    • Jitter generation and jitter tolerance exceed SGMII, XAUI and RXAUI specifications.
    • Serial output driver with calibrated on-chip termination resistor.
    • Selectable pre-emphasis level of signal at the output driver.
  • XAUI 10Gb Ethernet Attachment Unit Interface
    • XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
    • Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
    • Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
    • Aldec and ModelSim simulation models and test benches provided for free evaluation.
    Block Diagram -- XAUI 10Gb Ethernet Attachment Unit Interface
  • 10Gbps XAUI Transceiver
    • 10Gbps XAUI optimised for BP applications.
    • Alternate independent channel support for FC and Gigabit Ethernet.
    • Per channel rate of 1 to 3.125Gb/s.
    • High speed differential Reference CK.
  • XAUI PHY
    • Very low output jitter
    • Receiver equalization for enhanced jitter tolerance
    • Programmable TX levels with multiple post-cursor emphasis options
    • Automatic driver/receiver impedance calibration
    Block Diagram -- XAUI PHY
  • 10G XAUI/10GBase-KX4 Ethernet Verification IP
    • Follows 10G XAUI specification as defined in IEEE 802.3
    • Follows 10Gbase-KX4 specification as defined in IEEE 802.3
    • Supports backplane auto-negotation for 10GBASE-KX4
    • Supports all types of 10G XAUI/10GBase-KX4 TX and RX errors insertion/detection.
    Block Diagram -- 10G XAUI/10GBase-KX4 Ethernet Verification IP
  • XAUI/DXAUI
    • 8B10B encode/decode with error detection
    • Comma detection
    • RX elastic buffer/channel bonding
    • A state-of-the-art PMA (SERDES)
×
Semiconductor IP