The XAUI PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI applications. The XAUI PHY dwc_xaui3g_xN_pma_xN includes all the necessary logical, geometric, and physical design files to implement complete XAUI physical layer capability for 3.125-Gbps operation to connect a host or device controller to a XAUI system.
XAUI PHY
Overview
Key Features
- 3.125-Gbps transmissions rate
- Supports x4 configuration
- Integrated regulator to support either 3.3-V or 2.5-V I/O power supply
- Excellent performance margin and receiver sensitivity
- Robust PHY architecture that tolerates wide process, voltage, and temperature variations
- Low-jitter PLL technology with excellent supply isolation
- IEEE 1149.6 (AC JTAG) boundary scan
- Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester:
- Supports 3.125-Gbps test modes
- Advanced, built-in diagnostics including on-chip sampling scope for easy debug
- Visibility and controllability of hard macro functions through programmable registers in the design
- ? Overrides on all ASIC side inputs for easy debug
- ? Access register space through simple 16-bit parallel interface
- ? Access register space through JTAG port
Deliverables
- We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.
Technical Specifications
Foundry, Node
TSMC,40,65; SMIC,40; GF,40
Maturity
Silicon Proven
Availability
Immediate
GLOBALFOUNDRIES
Silicon Proven:
40nm
LP
SMIC
Silicon Proven:
40nm
LL
TSMC
Silicon Proven:
40nm
LP
,
65nm
LP