Ucie d2d adapter IP

The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer across the UCIe Link by seamlessly coordinating with the Protocol Layer and Physical Layer.
By minimizing logic on the main data path, it delivers a low-latency, optimized pathway for protocol Flits.

Compatible with UCIe v1.1 specification
Features single-ended, source-synchronous, and DDR I/O signaling
Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
Offers a high clock frequency up to 16GHz

Compatible with UCIe v1.0 specification
Single-ended, source synchronous and DDR IO Signaling
Supports 32 bits(16bits TX + 16bits RX) data bus per module for standard package
High clock frequency, up to 8GHz

Compliant with the UCIe specification (2.0 & 1.1)
Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)

The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and advanced mainband links and sideband links

Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics.
PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation.

UCIe D2D Adapter IP