Sidense OTP IP
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125
IP
from 33 vendors
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10)
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Vital signs healthcare sensor interface
- Two Channels of multi-lead electrocardiogram (ECG)
- Temperature sensor
- Differential capacitive sensor channel
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Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB PD 3.1 compliant.
- 8 bit register interface for a low speed processor, or optional I2C interface.
- Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
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SD4.1 UHS- II PHY IP
- SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
- 16bit interface to Link layer
- Supports both Full Duplex mode and Half Duplex mode
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Wi Fi PHY TestBench IP
- SoC architecture
- Scalable solution
- On demand customization available
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10/100/1000 MBit Ethernet MAC
- Full implementation of IEEE 802.3-2002
- 10/100/1000 MBit operation
- AMBA AHB host interface with DMA
- Low CPU overhead
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UHD Image Signal Processing (ISP) Pipeline
- Supports resolutions up to 7680x7680, including 4K2Kp60 (3840x2160)
- Input video formats: Raw Bayer, RGB and YCbCr; 8/10/12-bit per color
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10/100 Mbit Ethernet MAC
- Full implementation of IEEE 802.3-2002
- 10/100 Mbit operation
- AMBA AHB host interface with DMA
- Low CPU overhead
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800MHz General Purpose PLL
- Wide range M, P integer dividers.
- 50MHz – 800MHz output frequency range.
- Compare frequency range 8MHz – 32MHz.
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Gigabit Ethernet MAC with AVB
- Fully compliant with IEEE AVB (Audio Video Bridging) Standard
- Full-duplex mode at 10/100/1000 Mbps
- Half-duplex mode at 10/100 Mbps
- Supports IEEE 802.3-2008 compliant MII, RMII, SMII, GMII, RGMII, and SGMII
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CCSDS SCCC Encoder
- 4 state CCSDS compatible serially concatenated convolutional code (SCCC) encoder
- Code rates from 0.355 to 0.899
- Data lengths from 5758 to 43678 bits
- Interleaver sizes from 8640 to 65520 bits
