Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger

Overview

Key Features

• RISC-V RV32EC processor subsystem with debug module, JTAG debug transport, and instruction and data ROM and SRAMs
• Bandgap Vref/Ibias blocks that provide reference voltage and bias currents to analog blocks
• LDOs to derive power from the the external converter to power internal digital logic, analog blocks, and I/Os
• Power-on (PON) reset for digital blocks during power-supply ramp up and down
• 48MHz oscillator that provides the main clock for digital blocks
• 10kHz low power oscillator that provides a clock for the watchdog timer
• System control block that provides clock and reset control for digital logic, including clock gating
• System timer and watchdog timer
• I2C slave interface for test-access
• I2C slave controller for external host access
• I2C master interface for general purpose use
• I2C transceivers
• GPIO controller for outputs
• USB PD control and analog transceiver. The PD control implements PHY, protocol, and source policy engine layers.
• USB Type-C control and analog front end. The Type-C control implements the source state diagram.
• USB BC1.2 and QuickCharge 2/3/4 control and analog front end
• Power supply (PS) control and analog front end to control the setpoint for the external regulator, including slew-rate controlled transitions between voltages
• Current sense (ISNS) amplifier and control
• VBUS control and analog front end, including load-switch gate driver, discharge resistor, and voltage divider for VBUS measurement
• Monitoring control and analog front end for over-voltage, over-current, and reverse-current protection. The block includes comparators and interrupt request logic for fast response to faults.
• NTC thermistor and configuration resistor control and analog front end, driving source current into external resistors to generate a voltage to be measured by the ADC
• Multichannel SAR ADC control and analog front end, used to measure power supply voltage, VBUS voltage, current sense, thermistor temperature, and config resistor voltages
• One-time programmable (OTP) memory with controller for programming and read access
• Test access port with I2C slave interface
• Test control and trim registers
• Flexible Licensing Options
• Project based, Term, or Perpetual Licenses (Single Project or Multi-Project, Single Technology or Multi-Project/Multi-Technology)
• Manufacturing License options (GDS IP)

Block Diagram

Applications

• USB-C/PD Source-only port
• Battery charger

Deliverables

• Detailed data sheet and integration guide
• Synthesizable Verilog RTL source code
• ASIC digital synthesis constraints
• Complete analog IP in GDSII, including analog PHY
• FW source code
• FPGA development board with analog mezzanine card
• UVM based verification environment and test cases
• Design guide, programming user manual, and verification guide

Technical Specifications