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RapidIO IP

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Compare 23 IP from 10 vendors (1 - 10)
  • RapidIO Controller with V4.1 Support
    • Compliant to RapidIO Specifications revision 4.1
    • Compliant with RapidIO Error Management
    • Extension specification, Revision 4.1
    • Implements Logical, Transport and Physical layers functions
    Block Diagram -- RapidIO Controller with V4.1 Support
  • RapidIO to AXI Bridge (RAB)
    • Compliant with RapidIO specification, Revision 4.0
    • Compliant to AMBA AXI protocol v4
    • Supports 32-bit or 38-bit addressing
    • AXI PIO operation with configurable number of AXI Slaves
    Block Diagram -- RapidIO to AXI Bridge (RAB)
  • Serial RapidIO 2.1 Endpoint IP Core
    • LatticeECP3 AMC Evaluation board
    • Associated cables
    • AMC interface card
    • Demonstration bitstreams and files
    Block Diagram -- Serial RapidIO 2.1 Endpoint IP Core
  • Serial RapidIO - Physical Layer Interface
    • Supports High Speed 1x Mode (up to 2.5 Gbps)
    • 8B/10B Encoding and Decoding
    • Clock and Data Recovery (CDR)
    • Lane Synchronization
    Block Diagram -- Serial RapidIO - Physical Layer Interface
  • RapidIO PHY
    • 4 Channel per Quad
    • Shared Quad common PLL architecture
    • Digitally-control-impedance termination resistors
    • Configurable TX output differential voltage swing
  • RapidIO 2.0 PHY & Controller
    • One to Four independent 1.25/2.5/3.125Gbps per ports
    • Features as per RapidIO Specification revision v2.2
    • Precision low jitter master PLL and CDR loop
    • Supporting a 10 bit SerDes interface
  • RapidIO EndPoint Controller IP
    • Compliant with RapidIO Interconnect 2.2 specification
    • Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
    • Supports high link utilization and low latency
    • Supports efficient receive and transmit buffering scheme
  • LogiCORE IP Serial RapidIO Gen 2
    • 1x, 2x, & 4x Serial PHY - supports Artix-7, Kintex-7, Zynq-7000, Virtex-7, and Virtex-6 FPGAs
    • 1x, 2x & 4x Serial PHY - supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gbps line speed
    • Supports IDLE1 and IDLE2 sequence
    • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Serial RapidIO LogiCORE IP
    • 1x & 4x Serial PHY - Supports Virtex-6 LXT/SXT/HXT, Spartan-6 LXT, Virtex-5 LXT/SXT/FXT, and Virtex-4 FX FPGAs
    • 1x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0 Gpbs line speed
    • 1x & 4x Serial PHY - 64-bit internal data path
    • Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
  • Serial RapidIO Controller
    • Fully compliant with the RapidIO specification revision 2.2,
    • Simple transaction interface with Host processor and DMA Engine,
    • Configurable FIFOs implemented by BlockRAM in both transmit and receive paths,
    • Register file containing all necessary architectural registers providing total software control of IP core,
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