LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support For the Serial RapidIO Gen 2 Xilinx LogiCORE IP, please click here.
The LogiCORE IP Serial RapidIO Endpoint solution, designed to RapidIO Gen 1.3 specification with Gen 2 -5G line rate support, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) AND Transport Layer core. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.
The RapidIO Logical (I/O) and Transport Layer core and the RapidIO Physical Layer core, provide a complete Serial RapidIO protocol stack. Additionally, a highly optimized and configurable buffer design is included with these cores to implement a Serial RapidIO endpoint. While a modular IP design approach provides flexibility to enable ease of customization, the Xilinx tool chain automates generation of the serial endpoint on an FPGA by using these building block IP cores through a configurable and easy-to-use graphical user interface.
Serial RapidIO LogiCORE IP
Overview
Key Features
- 1x & 4x Serial PHY - Supports Virtex-6 LXT/SXT/HXT, Spartan-6 LXT, Virtex-5 LXT/SXT/FXT, and Virtex-4 FX FPGAs
- 1x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0 Gpbs line speed
- 1x & 4x Serial PHY - 64-bit internal data path
- Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
- Support for 8/16 bit device IDs, programmable source ID on all outgoing packets
- Doorbell and message support
- Support for priority based re-transmit suppression
- Independently configurable TX and RX buffer depths