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PCIe Gen4 IP

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Compare 29 IP from 11 vendors (1 - 10)
  • PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 16FFC, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 16FFC, N/S orientation
  • PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 16FFC, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 16FFC, N/S orientation
  • PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 12FFC, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 12FFC, N/S orientation
  • PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 12FFC, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 12FFC, N/S orientation
  • PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N7, 1.8V, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N7, 1.8V, N/S orientation
  • PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N6, 1.8V, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N6, 1.8V, N/S orientation
  • PCI Express Gen 4 PHY
    • Support 16GT 8GT 5GT 2.5GT data rate
    • Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
    • x1, x2, x4, x8, x16 lane configuration with bifurcation
    • Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
  • PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
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