The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS) capable of signaling at multiple data rates. The PHY supports multi-protocol market needs including a wide range of ac-coupled high-speed serial communication standards requiring serial Clock Data Recovery (CDR). Analog Bits’proprietary and industry leading PLL technology in combination with sophisticated circuit techniques and innovative IO design makes this macro an extremely area and power efficient solution.
The PHY includes a PCIe PCS, while featuring an additional interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 22.5Gbps. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.