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PAM4 Serdes IP

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Compare 33 IP from 13 vendors (1 - 10)
  • 112G-ULR PAM4 SerDes PHY
    • Supports full-duplex 1.25Gbps to 112.5Gbps data rates
    • Superior bit error rate (BER) performance across high-loss and reflective channels
    • Compliant with IEEE 802.3ck and OIF standard electrical specifications
    • Supports flexible SoC floorplan and IP placement and provides package substrate guideline/reference designs
  • 112G-ELR PAM4 SerDes PHY - TSMC 5nm
    • TSMC 5nm FinFET CMOS Process
    • Power-optimized for ELR and LR links
    • Integrated BIST capable of producing and checking PRBS
    • 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
  • 56G-LR Pam4 SerDes PHY
    • Supports Ethernet, FC, CPRI, and eCPRI protocols
    • Compliant to IEEE 802.3ck and OIF standard electrical specifications
    • Supports 56Gbps PAM4 and 28G, 10G, and sub-10Gbps NRZ data rates
    • Unique firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
    • Continuous calibration and adaption provide robust performance across process, voltage, and temperature
    • Supports industrial temperature range -40°C – 125°C
  • 112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
    • 1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
    • Power optimized for short-reach applications with configurability
    • Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
    • Beachfront optimized floorplan allows north-south and east-west SoC edge placement
    • Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
    • Enables 800Gbps networking with PHY and Controller solutions
    Block Diagram -- 112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
  • 1-56Gbps Serdes - 7nm (Multi-reference Clock)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (Ultra Low Latency)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (Area-optimized)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-112Gbps Serdes - 7nm
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (PPA-optimized)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 64G SerDes
    • 4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
    • Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
    • Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
    • Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades
    Block Diagram -- 64G SerDes
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