112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity

Overview

In data center interconnects, short-reach connectivity is needed in use-case scenarios for chip-to-chip, chip-to-optical-module, near-packaged optics, co-packaged optics or die-to-die. Power and area efficiency is critical in these use cases. The Cadence 112G-VSR PAM4 SerDes PHY provides optimized power, performance, and area (PPA) for short-reach to medium-reach applications at 1.25Gbps to 116Gbps data rates.

Key Features

1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
Power optimized for short-reach applications with configurability
Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
Beachfront optimized floorplan allows north-south and east-west SoC edge placement
Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
Enables 800Gbps networking with PHY and Controller solutions

Block Diagram

Applications

Communications
Data Processing

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist
f STA scripts for use at chip or standalone PHY levels
Liberty timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

TSMC 6nm,7nm

Maturity

Silicon proven

TSMC

Silicon Proven: 7nm

Request Info