112G-ELR PAM4 SerDes PHY

Overview

112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels for HPC SoCs.

The Cadence 112Gbps Extended Long-Reach (ELR) SerDes IP for TSMC 7nm/6nm operates at a full-rate of 112Gbps using PAM4 modulation and half-rate of 56Gbps using PAM4 modulation, as well as 56/28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The ELR PHY provides additional performance margin to highloss and reflective channels by incorporating reflection cancellation and enhanced digital signal processing. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links

Key Features

TSMC 7nm/6nm FinFET CMOS Process
Power-optimized for ELR LR and MR links
Fully autonomous startup and adaptation without requiring ASIC intervention
112/56Gbps PAM4 or 56/28/10Gbps NRZ data rates
Compact footprint for high-density designs
Compact footprint for high-density designs
Best-in-class DSP supports ELR lossy and reflective channels
Small area and low power is ideal for high port-density applications
Symmetric floorplan allows north-south and east-west SoC edge placement
Comprehensive on-chip diagnostic features make system testing/debugging quick and easy

Block Diagram

Applications

Communications
Data Processing

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist
f STA scripts for use at chip or standalone PHY levels
Liberty timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

TSMC 6nm,7nm

Maturity

Silicon proven

TSMC

Silicon Proven: 7nm

Request Info