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PAM-4 SerDes IP

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Compare 20 IP from 9 vendors (1 - 10)
  • 112G-ELR PAM4 SerDes PHY
    • Interoperability
    • Maximize beach front bandwidth
    • Layout flexibility
    Block Diagram -- 112G-ELR PAM4 SerDes PHY
  • 112G-ELR PAM4 SerDes PHY - TSMC 7nm
    • TSMC 7nm/6nm FinFET CMOS Process
    • Power-optimized for ELR LR and MR links
    • Fully autonomous startup and adaptation without requiring ASIC intervention
    • 112/56Gbps PAM4 or 56/28/10Gbps NRZ data rates
  • 112G-ELR PAM4 SerDes PHY - TSMC 5nm
    • TSMC 5nm FinFET CMOS Process
    • Power-optimized for ELR and LR links
    • Integrated BIST capable of producing and checking PRBS
    • 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
  • 56G-LR Pam4 SerDes
    • TSMC 7nm FinFET CMOS Process
    • 56Gbps PAM-4 or 28/10Gbps NRZ data rates
    • Power-optimized for LR and MR links
    • Compact footprint for high-density designs
  • 800 Gigabit Ethernet MAC + PCS
    • Two 400GBase-R PCS cores with required modifications and glue logic.
    • Includes RS-FEC(544,514) KP4 FEC
    Block Diagram -- 800 Gigabit Ethernet MAC + PCS
  • 64G SerDes
    • 4 Channels per Quad, <=64Gbps;
    • Serialization/Deserialization interface width;
    • Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines;
    • Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades;
  • 56G SerDes Ethernet
    • Data rate support up to 56Gbps (per lane)
    • Support the following protocols: 400GAUI-8, 400GAUI-16, CEI-56G-LR, CEI-56G-MR, CEI-56G-VSR, 40GBASE-CR4, 40GBASE-KR4, 100GBASE-CR10, 100GBASE-CR4, 100GBASE-KR4
    • Aggressive equalization capability to enable 56Gbps operation and legacy system upgrades
    • Variable AGC amplifier
  • SERDES PHY IP
    • Multi-protocol PHYs supporting data rate in the range of 1.25G to 10.3125Gbps
    • Support >20dB channel loss
    • Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration.
    • Support RX loss-of-signal detect
  • 1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
    • High speed performance
    • Low power architecture
    • Sub-sampling clock multiplier
    Block Diagram -- 1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
  • 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
    • Multi-protocol ePHY IP supports 1-56/112Gbps data rates
    • Low-Jitter Transmitter with 8-tap de-emphasis FIR
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Semiconductor IP