ONFI PHY IP
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31
IP
from 11 vendors
(1
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10)
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ONFI PHY 4.8GT/s for ONFI v6 & JESD230G
- Multi-interface support: ONFI6.0 up to 4800Mbps
- Multi-data-interface support: CTT (NVDDR3), LTT (NVLPDDR4) and PI-LTT
- Optimized for high performance and integration flexibility. The harden IP included 8-bit data blocks, up to 8 CE/channel, clock blocks, PLL, and DLL.
- High-resolution read/write delay adjust
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ONFI 5.1 PHY IP
- Compliant with ONFI 5.1 specification
- Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s
- Supports matched or unmatched DQS
- Supports WDCA/Per-Pin VREFQ Training for NAND devices
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ONFI 5.0 PHY IP
- Compliant with ONFI 5.0 specification
- Supports NV-DDR2 mode
- Supports NV-DDR3, NV-LPDDR4, with a maximum rate of 2400MT/s
- Supports PHY Independent TX/RX Training mode
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ONFI 5.0 PHY
- The PHY design supports the newly introduced NV-LPDDR4 mode along with SDR, NV_DDR, and NV_DDR2, NV_DDR3 mode.
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ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
- Support ONFi 4.0 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 with operating frequency up to 533Mbps
- Support NV-DDR3 with operating frequency up to 800Mbps
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ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
- Support ONFi 4.1 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 up to 533Mbps
- Support NV-DDR3 up to 1200Mbps
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ONFI 3.2 NV-DDR2 PHY in GDSII
- Compliant to ONFI revision 3.2 standard
- Supports NV-DDR2 mode of operation supporting up to 266MHz or 566MT/s
- Supports NV-DDR mode of operation supporting up to 100MHz
- Supports legacy Asynchronous devices operating from 10MHz to 50MHz
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
