The ONFI IP provides Turnkey solutions for IC requiring access to ONFI-compatible NAND Flash devices. Optimized for low power and high-speed applications, it features robust timing and a compact silicon area. It supports all ONFI NAND Flash components available on the market. The PHY includes critical timing synchronization modules (TSM) specialized for utility and functionality and low power/jitter DLLs with programmable fine-grain control for any NAND Flash interface.
The AXI interface ONFI provides four AXI channels to connect to the ONFI PHY, ensuring compliance with the DFI digital interface specifications. It employs a two-layer architecture, making the interface flexible and easily adaptable to various multi-port bus formats and timing sequences. One layer consists of the CPU bus core, which supports single or a multi-port CPU buses, while the other layer is the controller core responsible for communication with the DFI PHY. Between these layers, the TX/RX data FIFOs and a generic command FIFO are utilized to isolate the internal controller from changes of the CPU bus core.
The overall design of the IP solution is versatile, lightweight, and easily adjustable to different CPU bus ports. It achieves high efficiency within a compact design. All interface timings on DFI and controller are in 1x SDR clock domain which can run at half the speed of the PHY core. The interface is highly generic and supports high-performance input and output data flow, reaching up to 4800Mbps ONFI speeds in a wide range.
