Northwest Logic IP
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5,370
IP
from 212 vendors
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10)
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JESD204D Transmitter and Receiver IP
- Designed according to JEDEC JESD204D Standard.
- Supports up to 24 lanes per IP cores.
- Supports new link layer using Reed-Solomon Forward Error Correction (RS-FEC).
- Option for backward compatibility to JESD204C (supports 64B/66B encoding) and JESD204B (supports 8B/10B encoding).
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ARINC 818-3 IP Core
- Compliant to ARINC818-3 Specification. The max speed supported is 28 Gbps.
- Built on Fiber Channel Audio Video protocol.
- Point-to-Point Video/Data Transmission support using 64B/66B and 256B/257B Encoding over the serial link.
- Supports both optical and electrical links.
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32x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V Logic Process
- Fully compatible with MXIC 0.18um 1.8V/5V logic process
- Wide operating voltage range:
- – Read voltage: 2.5-5.5V VDD and VDDP
- – Program Voltage: 5V+/-10% VDDP and 2.5-5.5V VDD
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32x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V Logic Process
- Fully compatible with MXIC 0.18um 1.8V/5V logic process
- Wide operating voltage range:
- – Read voltage: 2.5-5.5V VDD and VDDP
- – Program Voltage: 5V+/-10% VDDP and 2.5-5.5V VDD
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64x8 Bits OTP (One-Time Programmable) IP, Nexchip 0.15um 3.3V Logic Processes
- Fully compatible with Nexchip 0. 15um 3.3V logic processes
- Wide operating voltage range:
- – Read voltage: 1.62–3.63 V VDD and VDDP
- – Program Voltage: 3.45 V ± 5% VDDP and 1.62–3.63 V VDD
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32x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V Logic 18A Process
- Fully compatible with MXIC 0.18um 1.8V/5V logic 18A process
- Wide operating voltage range:
- – Read voltage: 2.5-5.5V VDD and VDDP
- – Program Voltage: 5V+/-10% VDDP and 2.5-5.5V VDD
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64x8 Bits OTP (One-Time Programmable) IP, CanSemi 0.18um 1.8V/3.3V Logic Process
- Fully compatible with CanSemi 0.18um 1.8V/3.3V logic process
- Wide operating voltage range: 1.62V-3.63V read voltage, 3.6V+/-5% program voltage
- High speed: 10µs program time per bit
- Wide temperature: -40°C to 125°C for read and 10°C to 40°C for program
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64x8 Bits OTP (One-Time Programmable) IP, UMC 55nm ULP standard CMOS core logic Process
- Fully compatible with standard 55nm ULP CMOS core logic process
- Low voltage: 0.95 V ± 10% read voltage, 1.5 V ± 0.1V program voltage
- High speed: 10-µs program time per bit, and 200-ns cycle time read
- Wide temperature: from -40°C to 125°C
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Embedded EEPROM IP, 4096x1 bits for 1.8V/3.3V Logic
- Logic Embedded IP
- Programming with FN program, erasing with FN erase
- High yield performance
- Small IP size
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Embedded OTP (One-Time Programmable) IP, 512x16 bits for 1.8V/3.3V Logic
- Logic Embedded IP
- Programming with channel hot electron injection, erasing with UV illumination
- High yield performance
- Small IP size