JESD204D Transmitter and Receiver IP

Overview

The main goal of this JEDEC Standard, JESD204D is to increase the lane rates to support even higher bandwidth applications needs and to add extra features.

It is designed to have backward-compatibility options to JESD204C and JESD204B. Logic Fruit is a leader in JESD IPs and provides FPGA based solutions that works with leading ADCs/DACs from different vendors. We have been at the forefront in implementing JESD204B and JESD204C protocols with adoptions from Tier1/2 vendors worldwide. Logic Fruit is continuing its innovations as the pioneer for JESD204D IPs on FPGAs.

Key Features

Designed according to JEDEC JESD204D Standard.
Supports up to 24 lanes per IP cores.
Supports new link layer using Reed-Solomon Forward Error Correction (RS-FEC).
Option for backward compatibility to JESD204C (supports 64B/66B encoding) and JESD204B (supports 8B/10B encoding).
Transport layer to support multi ADC/DAC synchronization and multiple lanes.
Data interfaces up to 116 Gbps with PAM4 encoding and up to 58 Gbps with NRZ encoding.
Supports subclass 0, 1 and 3.
Supports all the new features introduced in JESD204D specifications.

Benefits

With the addition of error correction and Detection(FEC, CRC), cutting-edge instrumentation and other applications can operate without any errors.
Offers better DC balance, clock recovery and data alignment compared to JESD204B.
The bit overhead is 3.125% which is much smaller than JESD204B (~ 25%).
Provides interface for serializing devices from some system designs, reducing space, power, and cost.
It supports interface requirements of high megabit and Gigabit data rates for various applications such as 5G cellular equipments, test equipments, medical devices, military warfare and so on.
Mechanism to achieve Deterministic latency across the serial link.

Block Diagram

Technical Specifications

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