MIPI CSI-2 v3.0 IP

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Compare 8 IP from 5 vendors (1 - 8)
  • MIPI CSI-2 v3.0 Rx/Tx For Combo C/D-PHY
    • Compliant with MIPI CSI Standard v3.x, v2.x , v1.x and MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
    Block Diagram -- MIPI CSI-2 v3.0 Rx/Tx For Combo C/D-PHY
  • MIPI CSI-2 v3.0 TRANSMITTER FOR COMBO C/DPHY
    • Compliant with MIPI CSI Standard v3.x, v2.x, v1.x and MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C- PHY V1.x
    • Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios.
    • Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
    • Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration.
    Block Diagram -- MIPI CSI-2 v3.0 TRANSMITTER FOR COMBO C/DPHY
  • Simulation VIP for MIPI CSI-2
    • PHY Interfaces
    • Supports D-PHY v2.5, C-PHY v2.0 and A-PHY v1.0 with both PHY interfaces: Serial (Dpdn/ABC/Uplink/downlink) and Parallel (PPI/APPI)
    • PPI Data Bus Width
    • Supports 16- and 32-bit PPI data bus width over C-PHYsm
    Block Diagram -- Simulation VIP for MIPI CSI-2
  • MIPI CSI-2 Verification IP
    • Full MIPI CSI2 Tx/Rx functionality
    • Compliant with MIPI CSI2 Bus Specification v1.0 to v1.3, v2.0 to v2.10,v3.0,v4.0.
    • Supports both DPHY and CPHY.
    • Supports forward escape ULPM on all Data Lanes.
    Block Diagram -- MIPI CSI-2 Verification IP
  • MIPI CSI-2 Synthesizable Transactor
    • Supports 3.0 MIPI CSI-2 Specification.
    • Compliant with MIPI CSI2 Bus Specification v1.0 to v1.3, v2.0 to v2.10, v3.0.
    • Full MIPI CSI2 Tx/Rx functionality
    • Support both DPHY and CPHY.
    Block Diagram -- MIPI CSI-2 Synthesizable Transactor
  • MIPI CSI-2 RX Controller
    • Low power consumption
    • Small footprint
    • Complete function verification through VIP
    Block Diagram -- MIPI CSI-2 RX Controller
  • GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
    • GLOBALFOUNDARIES 22nm FDSOI 0.8V/1.8V
    • 80 to 6000 Mbps data rate per lane in DPHY HS mode
    • 0 to 4500 Msps symbol rate per lane in CPHY HS mode
  • GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
    • Process: GLOBALFOUNDARIES 22nm FDSOI 0.8V/1.8V
    • 80 to 6000 Mbps data rate per lane in DPHY HS mode
    • 80 to 4500 Msps symbol rate per lane in CPHY HS mode
    • All lanes support HS and ULPS modes in forward direction
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Semiconductor IP