MIPI CSI-2 v3.0 TRANSMITTER FOR COMBO C/DPHY
Key Features
- Compliant with MIPI CSI Standard v3.x, v2.x, v1.x and MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C- PHY V1.x
- Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios.
- Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
- Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration.
- Configurable up to 4 Virtual Channels
- Operate in continuous and non-continuous clock modes.
- Color Modes: 16, 18, 24 and 36 bpp
- Color Formats: YUV420 8, 10bits and without CSPS and Legacy, YUV422 8, 10bits, RGB-888, 565, 666, 555 and 444. RAW6, 7, 8, 10, 12 and 14.
- Register configuration through CCI interface
- Host Interface can be Pixel or AXI interface.
Block Diagram
Technical Specifications
Maturity
Silicon Proven, FPGA Validated, Interop tested, Design Verified
Availability
Immediately