Low Power Memory Compiler IP
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Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
- Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
- Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power
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Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Foundry sponsored memory generator
- For nominal voltage characterization corner
- Configuration
- Dolphin's SVT bit-cell and HVT transistors for periphery
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
- Foundry sponsored memory generator
- For nominal voltage characterization corner
- Power reduction features
- Up to 50% gain in dynamic power consumption compared to standard ROM
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Ultra-low-leakage even in a generic process
- No leakage in memory plane
- Minimal leakage in memory periphery while achieving between 230 and 300 MHz in worst case in TSMC 90 nm LP !
- Key patent for high density with only one programming layer
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
- Power reduction features
- Decrease of packaging cost
- Smaller SoC area
- Decrease of fabrication costs