IP Catalog > Interface IP > Memory Interface IP > LPDDR IP > LPDDR4 IP > LPDDR4 Controller IP > LPDDR4 Assertion IP

LPDDR4 Assertion IP

Overview

LPDDR4 Assertion IP provides an efficient and smart way to verify the LPDDR4 designs quickly without a testbench. The SmartDV's LPDDR4 Assertion IP is fully compliant with standard LPDDR4 Specification.

LPDDR4 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR4 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Supports 100% of LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y(Proposed).
    • Supports all the LPDDR4 commands as per the specs.
    • Quickly validates the implementation of the LPDDR4 standard JESD209-4,JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y (Proposed).
    • Supports for all mode registers programming.
    • Supports for Programmable READ/WRITE Latency timings.
    • Supports for both 16 and 32 Programmable burst lengths.
    • Supports for the following Burst Type,
    • Sequential
    • Supports for Burst sequence.
    • Checks for following
    • Check-points include power up,initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
    • Supports for Write data mask and data strobe features.
    • Supports for Write and Read DBI.
    • Supports for Write leveling.
    • Supports for CA training.
    • Supports for ODT(On-Die Termination) features.
    • Supports for ZQ Calibration commands.
    • Supports for DQ Calibration.
    • Supports for DQ Vref training.
    • Supports for Byte mode.
    • Supports for Power Down features.
    • Supports for Self refresh.
    • Supports for Refresh management.
    • Supports for all types of timing and protocol violation detection.
    • Supports for full-timing as well as behavioral versions in one model.
    • Supports for all timing delay ranges in one model: min, typical and max.
    • Protocol checker fully compliant with LPDDR4 Specification JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4D, JESD209-4X and JESD209-4Y (Proposed).
    • Constantly monitors LPDDR4 behavior
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV LPDDR4 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure LPDDR4 Assertion IP functionality.

Benefits

  • Runs in every major formal and simulation environment.

Block Diagram

LPDDR4 Assertion IP Block Diagram

Deliverables

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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