LEON3 IP
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32-bit SPARC V8 processor
- SPARC V8 compliant integer unit with 7-stage pipeline
- Hardware multiply, divide and MAC units
- Interface to FPU and custom co-processors
- Separate instruction and data cache (Hardvard architecture)
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32-Bit SPARC V8 Processor
- SPARC V8 instruction set with V8e extensions and compare-and-swap
- Advanced 7-stage dual-issue pipeline
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Fault-tolerant 32-bit SPARC V8 processor
- Register file SEU error-correction of up to 4 errors per 32-bit word
- Cache memory error-correction of up to 4 errors per tag or 32-bit word
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Single- and double-precision IEEE-754 floating-point unit
- IEEE-754 compliant, supporting all rounding modes and exceptions
- Operations: add, subtract, multiply, divide, square-root, convert, compare, move, abs, negate
- Data formats: single and double precision (32- and 64-bit floats)
- Fully pipelined, 3 clock cycles latency for all operations except divide and square-root
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Bi-directional AMBA AHB/AHB bridge
- AMBA AHB master and AHB slave interfaces
- Bi-directional communication, allows masters on either bus side
- Handles single and burst transfers in both directions
- Internal FIFOs for data buffering