The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
Configurable AMBA bus SoC platform
Overview
Key Features
- Robust and fully synchronous single-edge clock designs
- Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
- Fault-tolerant and SEU-proof version
- Symmetric Multi-processor support (SMP)
- Extensively configurable
- Large range of software tools: compilers, kernels, simulators and debug monitors
- IP cores:
- LEON3 processor,SPARC V8 instruction set with V8e extensions
- Hardware multiply, divide and MAC units
- Local instruction and data scratch pad rams
- SPARC Reference MMU (SRMMU) with configurable TLB
- AMBA controller with round robin arbiter
- AMBA to APB bridge
- AHB to AHB bridge
- Advanced on-chip debug support with instruction and data trace buffer
- Fully pipelined IEEE-754 FPU
- SRAM, SDRAM and DDR controllers
- 32-bit Master/Target PCI
- 10/100/1000 Ethernet MAC
- CAN interface
- SpaceWire interface
- Mil-std-1553 interface
- Advanced Encryption Standard (AES)
- Elliptic Curve Cryptograph (ECC)
- ATA Controller
- VGA Controller
- PS2 and keyboard
- GPIO
- Timers
- UARTs
- Interrupt controller
Benefits
- Available in GPL for evaluation
- Low cost commercial license
- Easily prototyped on low-cost FPGA boards
- Low area
Technical Specifications
Maturity
Production
Availability
Now