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JESD204D IP

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Compare 7 IP from 4 vendors (1 - 7)
  • JESD204D Verification IP
    • Truechip JESD204D VIP is compliant to the latest JESD204D,C.01,C &B specification by JEDEC
    • It is also backward compatible with all the previous versions of JESD204
    • Supports a wide range configurations for data converter devices
    • Over single and multiple serial links with each link can support single or multiple lanes as per requirements
    Block Diagram -- JESD204D Verification IP
  • JESD204D Transmitter and Receiver IP
    • Designed according to JEDEC JESD204D Standard.
    • Supports up to 24 lanes per IP cores.
    • Supports new link layer using Reed-Solomon Forward Error Correction (RS-FEC).
    • Option for backward compatibility to JESD204C (supports 64B/66B encoding) and JESD204B (supports 8B/10B encoding).
    Block Diagram -- JESD204D Transmitter and Receiver IP
  • JESD204D Controller IP
    • Line rates up to 116 Gbps
    • Supports 1-24 lanes
    • Supports 1-96 converters
    • HD-mode supported
    Block Diagram -- JESD204D Controller IP
  • JESD204 Verification IP
    • This JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
    • The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product.
    Block Diagram -- JESD204 Verification IP
  • JESD204 Verification IP
    • Follows JESD204 specification JESD204A, JESD204B, JESD204C and JESD204D.
    • Supports Transmitter and Receiver Mode.
    • Supports data interfaces up to 116 Gbps with PAM4 and up to 58 Gbps with PAM2 in PHY layer.
    • Supports up to 32 lanes.
    Block Diagram -- JESD204 Verification IP
  • FEC RS (544,514) IIP
    • Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (544,514) FEC, 10-bit symbols.
    • Supports different input and output data widths of multiples of 10-bits.
    Block Diagram -- FEC RS (544,514) IIP
  • FEC RS (528,514) IIP
    • Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (528,514) FEC, 10-bit symbols.
    • Supports different input and output data widths of multiples of 10-bits.
    Block Diagram -- FEC RS (528,514) IIP
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