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JESD204 Verification IP

Overview

JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC. JESD204A/B/C/D VIP can be used to verify transmitter or Receiver device following the JESD204 basic protocol as defined in JESD204. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

JESD204 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

JESD204 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Follows JESD204 specification JESD204A, JESD204B, JESD204C and JESD204D.
  • Supports Transmitter and Receiver Mode.
  • Supports data interfaces up to 116 Gbps with PAM4 and up to 58 Gbps with PAM2 in PHY layer.
  • Supports up to 32 lanes.
  • Supports 32bit data width per converter.
  • Supports up to 256 converters per transmitter & receiver BFM.
  • Scrambler can be enabled or disabled.
  • Supports 8b/10b link layer functions.
  • Supports 64b/66b link layer functions based on IEE802.3 Clause 49 and JESD204C.
  • Supports 64b/80b link layer functions with fill bit encoding based on IEEE802.3 clause 49 and JESD204C.
  • Supports new link layer with Five types of RS-FEC modes based on IEE802.3 Clause 91.
    • FEC1 - (136,130)
    • FEC2 - (144,130)
    • FEC3 - (272,258)
    • FEC4 - (544,514)
    • FEC5 - (528,514)
  • Supports Forward Error Correction (FEC) and command channel.
  • Supports following cyclic redundancy checks(CRC) encoding in JESD204C.
    • CRC-3
    • CRC-12
  • Supports single block, Multi block and extended multi block.
  • Supports new schemes for FEC, frame, and lane alignment.
  • Supports Forward Error Correction (FEC).
    • fec_encoding
    • fec_decoding
  • Supports payload symbols, payload block and alignment block and fec codwords.
  • Provides error injection and error detection with a wide variety of error types. Which includes,
    • Invalid code group insertion
    • Disparity errors
    • CRC errors
    • Sync error insertion
    • Lane skew insertion
    • FEC errors
    • Scrambler error insertion
  • Supports constraints Randomization.
  • Functional coverage to cover each and every feature of the JESD204 specification.
  • Test suite to test each and every feature of JESD204 specification.
  • Callbacks monitor, transmitter and receiver for various events.
  • Status counters for various events on bus.

Benefits

  • Faster testbench development and more complete verification of JESD204 designs.
  • Easy to use command interface simplifies testbench control and configuration of TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

JESD204 Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the JESD204 testcases.
  • Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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