FEC RS (544,514) IIP

Overview

Key Features

• Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
• Supports full FEC functionality.
• Supports Reed Solomon (544,514) FEC, 10-bit symbols.
• Supports different input and output data widths of multiples of 10-bits.
• Supports the parity generation of 300 bits.
• Supports the bit locker mechanism.
• Supports the Syndrome calculation.
• Supports the Berlekamp's algorithm.
• Supports the Chien search for error position.
• Supports the Error correction of 150 bits.
• Supports up to the 15 symbols of error correction.
• Supports the pipelined mechanism for the error correction.

Benefits

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

• The FEC RS (544,514) interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• Documentation contains User's Guide and Release notes.

Technical Specifications