Interlaken c2c controller IP

Support for up to 600 Gbps of throughput
Data striping and de-striping across 1 to 24 lanes
Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types

The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.

The lane logic only mode allows each serial transceiver to be used to build a fully featured Interlaken interface. In devices with 48 serial transceivers, up to 600 Gb/s of total throughput can be sustained.
The protocol logic supported in each integrated IP core scales up to 150 Gb/s. The Interlaken integrated IP core solution is designed to be compliant with Interlaken Protocol Definition, Revision 1.2, October 7, 2008.
The integrated IP core implements both the lane logic and protocol logic portions of the specification, which saves approximately 60k+ System Logic Cells per instantiation and uses about 1/8th the power of equivalent soft implementations.

Local serial loop-back from transmitter to receiver at serial transceiver for self test

Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input

Interlaken C2C Controller IP