ISO 26262 RISC-V IP
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9
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from 6 vendors
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RISC-V CPU IP With ISO 26262 Full Compliance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Bit-manipulation extensions
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32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- Flexible use cases
- roven technology
- State-of-the-art safety and security
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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32 Bit - Embedded RISC-V Processor Core
- Best-in-class performance for small-area and low-power applications
- Highly configurable and easy and quick to customize and verify
- Process compliant with ISO 26262 and ISO 21434
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32-bit Embedded RISC-V Functional Safety Processor
- Designed for Functional Safety
- Efficient Embedded RISC-V Processor
- Powerful Debug Features
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ARC-V RMX Series Functional Safety Processor IP
- Developed for full ASIL D compliance (systematic and random faults)
- Tightly-coupled dual-core safety implementation based on ultra-compact ARC-V RMX processors
- Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single-core operation (RMX-510-FS only)
- Integrated hardware safety features including ECC, user-programmable windowed watchdog timer, end-to-end protection (E2E) for buses/data-path, and lockstep safety monitor
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Integrated Secure Element (iSE) for high-end devices with HW isolated secure processing
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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Integrated Secure Element (iSE) for automotive
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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Ncore 3 Coherent Network-on-Chip (NoC)
- Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
- AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
- Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
- Configurable last-level caches
