GLink IP
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11
IP
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10)
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TSMC CLN5FF GLink GPIO
- 18 full-duplex lanes for die to die connections
- 2 redundant lanes for repair
- Maximum speed 500 Mbps
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GLink Multi-Slice PCS
- Align data buses of different GLink Slices
- Compatible with any revision of GLink IP
- VALID and READY handshake mechanism
- Support any data bus width
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GLink CXS-Bridge
- Provide AMBA CXS issue-B compliant user interface
- Align data from multiple GLink Slices
- Compatible with any revision of GLink IP with PCS-replay enabled
- Provide pairing of TX and RX CXS-Bridge
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GLink AXI Wrapper
- Supports user interface of AMBA AXI3/AXI4 compliant bus
- Align data buses of different GLink Slices
- Compatible with any revision of GLink IP with PCS-replay feature
- Provide pairing of TX and RX AXI Wrapper
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GLink Multi-Slice PCS
- Align data buses of different GLink Slices
- Compatible with any revision of GLink IP
- VALID and READY handshake mechanism
- Support any data bus width
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TSMC CLN5FF Glink 2.0 Die-to-Die PHY
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- VALID and READY handshake mechanism
- Flow control between TX and RX
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TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
- 56 full-duplex lanes per slice
- 6-Slice/2-Slice PMA included in the analog hard macro
- Lane repair
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TSMC CLN5FF GLink 2.0 Die-to-Die PHY
- 32 full-duplex lanes per slice
- 8 slices are included in the analog hard macro
- 1:8 mode with 256-bit data width or 1:16 mode with 512-bit data width for user interface
- VALID and READY handshake mechanism
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TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
- 56 full-duplex lanes per slice
- 8 slices are included in the analog hard macro
- 1:8 mode with 448-bit data width or 1:16 mode with 963-bit data width for user interface
- VALID and READY handshake mechanism
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TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
- Supports SoIC (3DFabric) CoW and WoW assembly
- Supports face to face and face to back with the same GDSII