TSMC CLN5FF GLink GPIO
Overview
IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initialization sequence. The IP is ready for operation immediately after reset; therefore it could be used to transfer configuration and control buses (I2C, SPI, etc.) across two dies. IGID2DY01A GPIO performs an 18-pair lane connection.
Key Features
- 18 full-duplex lanes for die to die connections
- 2 redundant lanes for repair
- Maximum speed 500 Mbps
- Supports internal loopback test
- EHOST: APB, I2C, and JTAG register interface
- Share 0.75 V typical AVDD power with GLink Slice
- Operating junction temperature: -40 °C ~ 125 °C
- Process: TSMC 5 nm 0.75 V/1.2 V CMOS LOGIC FinFET Process
- Metal Scheme: 1P16M (1X_h_1Xb_v_1Xe_h_1Ya_v_1Yb_h_4Y_vhvh_2Yy2Yx2R)
- Analog hard macro size: 746.283 um x 183.988 um for horizontal macro (E-W orientation) and
- 183.957 um x 745.640 um for vertical macro (N-S orientation)
- Supports both horizontal and vertical GDS orientation
- Special Layer & Device: High R Resistance and ULVT
Technical Specifications
Foundry, Node
TSMC 5nm CLN5FF
Maturity
Avaiable on request
TSMC
Pre-Silicon:
5nm