IP Catalog > Fibre Channel

Fibre Channel IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (19)
Compare 19 IP from 9 vendors (1 - 10)
  • Fibre Channel ULP (Upper Layer Protocol) Core
    • FC-AE-RDMA & FC-AV compliant interface with hardware-based offload
    • Hardware DMA engines map sequence data to host memory buffers
    Block Diagram -- Fibre Channel ULP (Upper Layer Protocol) Core
  • Fibre Channel ASM (Anonymous Subscriber Messaging) Core
    • Message label validation checks performed in hardware
    • Multiple user modes for receiving messages, including strictly mapped message-to-buffer and free-buffer implementations
    • Transmit message chaining options provided
    • Complete set of registers for managing core and configuring core options
    Block Diagram -- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
  • Fibre Channel Link Layer Core
    • Complete FC1-FC2 functionality
    • Intuitive streaming user interface
    • Scales for multiple port designs
    Block Diagram -- Fibre Channel Link Layer Core
  • 32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
    • Low latency design
    • Configuration and status bus
    • Example reference design demonstrating of RS-FEC and GT Wizard cores
    • ECC RAM option
  • 1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes
    • Quad SerDes optimized for Fibre Channel and backplane applications
    • Supports data rates from 1.0625/2.125 and 4.25 Gbps speeds
    • High-speed differential reference clock
    • Low jitter clock synthesizers for clock distribution
  • 25Gbps Ethernet and CPRI-10 FEC Layer IP Core
    • Proven IP reduces development time and risk
    • Upgrade process as the standard evolves
    • Supports both 25GBASE-KR and 25GBASE-CR PMD interfaces
    Block Diagram -- 25Gbps Ethernet and CPRI-10 FEC Layer IP Core
  • Digital Video Broadcasting - (DVB-ASI) IP Core
    • Configurable Tx FIFO supporting independent Layer 2 transmit clock
    • Configurable Rx FIFO supporting independent Layer 2 receive clock
    • Automatic start of packet comma insertion in the transmit side
    • Rate-matching comma insertion in the transmit side
    Block Diagram -- Digital Video Broadcasting - (DVB-ASI) IP Core
  • 3.25 Gigabit SerDes
    • 1.0 to 3.25 Gbps operation per channel
    • 1.2V power supply, CMOS design
    • Low power dissipation
    • Minimal external components
    Block Diagram -- 3.25 Gigabit SerDes
  • 4.25 Gbps Quad Multistandard SerDes
    • 1.0 to 4.25 Gbps operation per channel
    • 1.2V/2.5V power supply, CMOS design
    • Low power dissipation (80mW /channel at 3.2 Gbps)
    • Minimal external components
    Block Diagram -- 4.25 Gbps Quad Multistandard SerDes
  • IEEE 802.3 Clause 74 FEC
    • The IP core supports encoding and decoding of the (2112,2080) Fire code defined in IEEE 802.3 Clause 74
    • Suitable for 10GBASE-R, 25GBASE-R, 40GBASE-R, 50GBASE-R and 100GBASE-R Ethernet PHYs and 16G Fibre Channel PHYs
    • Burst errors of up to 11 bits can be corrected
    • All alignment, transcoding, and scrambling functions are performed within the core
×
Semiconductor IP