Fibre Channel Verification IP

Overview

Fibre Channel Verification IP provides an smart way to verify the Fibre channel MAC, PCS and serdes of a SOC or a ASIC. The SmartDV's Fibre Channel verification IP is fully compliant with standard Fibre channel Specification (FC-FS-6 Rev 0.1, FC-LS-4 Rev 4.03, FC-PI-7 Rev 0.13) and provides the following features.

Fibre Channel Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Fibre Channel Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with the Fibre Channel framing and signaling specification FC-FS-6, Rev 0.1.
Compliant with the Fibre Channel link service specification FC-LS-4, Rev 4.03.
Compliant with the Fibre Channel physical interface specification FC-PI-7, Rev 0.13.
Compliant with the Fibre Channel protocol for SCSI specification FCP-4.
Compliant with SCSI Architecture Model 3/4/5 (SAM-3/4/5).
Supports following interfaces

1 bit (serial) and 8,10,20,32,40,64 bit (parallel)
8B/10B,64B/66B,256B/257B Encoder/Decoder interface
32 bit Dword Primitive interface
Dword level transport interface
Complete Frame transaction level interface

Supports 256GFC, 128GFC, 64GFC, 32GFC, 16GFC, 8GFC, 4GFC, 2GFC and 1GFC.
Supports speed switching/negotiation.
Supports L, N, and F ports.
Supports multiple initiators and multiple targets.
Supports generation of all types of FC frames.
Supports verification of all layers of Fibre Channel.
Supports Port/Process/Fabric Login/Logout.
Supports Transmitter training.
Supports Forward Error Correction (FEC).
Supports Energy Efficient Fibre Channel.
Supports all SCSI commands.
Supports multiple outstanding exchanges.
Supports several queuing attribute models.
Supports Multiple Logical Unit Number (LUN) addressing.
Supports completely configurable target/device discovery.
Supports error detection and recovery management.
Supports all type of FC timers.
Supports error injection and detection at each layer

Invalid frame fields
Invalid EOF and SOF
Oversize and undersize frames
Disparity errors
Invalid code group errors
Invalid K and D character
CRC error.

Supports Retry control.
Proficiency to generate random frames and respond to frames in directed or randomized fashion.
Rich set of configuration parameters to control Fibre Channel functionality.
Monitors, detects and notifies the test bench of all protocol and timing errors.
Supports constrained randomization of protocol attributes.
Status counters for various events.
Callbacks in initiator, target and monitor for various events.
Fibre Channel Verification IP comes with complete test suite to test every feature of Fibre Channel specification.
Functional coverage for complete Fibre Channel features.

Benefits

Faster test bench development and more complete verification of FC Designs.
Easy to use command interface simplifies test bench control and configuration of initiator, target and monitor.
Simplifies results analysis.
Integrates easily into OpenVera, SytemVerilog,SystemC,Verilog
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the Fibre Channel testcases.
Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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