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CSI-2 Controller IP

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Compare 137 IP from 14 vendors (1 - 10)
  • MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
    • Fully compliant to MIPI standard
    • Small footprint
    • Code validated with Spyglass
    Block Diagram -- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
  • MIPI CSI-2 Controller Core V2
    • Fully CSI-2 standard compliant
    • 64 and 32 bit core widths
    • Transmit and Receive versions
    Block Diagram -- MIPI CSI-2 Controller Core V2
  • MIPI CSI-2 TX IP
    • Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) V1.3
    • Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
    • Integrated PHY Protocol Interface (PPI) interfaces to CSI-2 and UniPro™ MIPI® protocols
    • HS, LP and ULPS modes supported
  • MIPI CSI-2 RX IP
    • Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) V1.3
    • Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
    • Integrated PHY Protocol Interface (PPI) interfaces to CSI-2 and UniPro™ MIPI® protocols
    • HS, LP and ULPS modes supported
  • MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
    • Fully compliant to MIPI standard
    • Small footprint
    • Code validated with Spyglass
    Block Diagram -- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
  • MIPI CSI2 Transmit Controller
    • Camera Serial Interface (CSI-2) version 1.1
    • D-PHY version 1.1
    • CSI-2 interface on device side supports
    • AMBA APB Slave for Control and Status
    Block Diagram -- MIPI CSI2 Transmit Controller
  • MIPI CSI-2 RX Controller
    • Low power consumption
    • Small footprint
    • Complete function verification through VIP
    Block Diagram -- MIPI CSI-2 RX Controller
  • MIPI CSI-2 TX Controller for v2.1
    • Compliant with MIPI CSI-2 v2.1 Specification
    • Provides up to 4 independent stream input interfaces, with a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, and Data Type interleaving
    • RTE – Efficient Packet Delimiter support (Option 1 and 2)
    • Programmable Data Type and Word Count settings, with either 8 or 16 options selectable on a packet-bypacket basis
  • MIPI D-PHY CSI-2 RX IP
    • Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) V1.3
    • Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
    • 2.5Gbps maximum data transfer rate per lane (D-PHY)
    • Implements all four CSI-2 MIPI Layers (PHY Layer, Lane Management Layer, Low Level Protocol and Byte to Pixel Unpacking Formats)
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Semiconductor IP