MIPI CSI-2 RX Controller

Overview

CSI-2 receiver controller for application processor

The Cadence^® Receiver (RX) IP for MIPI^® CSI-2^sm is a fully verified, configurable, digital core that is compliant with the MIPI Alliance CSI-2 v2.1 specification. The Controller IP is responsible for handling and decoding CSI-2 protocol-based camera or other sensor data stream and managing the forwarding or unpacking of payload data to the pixel-stream interfaces. It is an ideal solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.

Key Features

Standards Compliant. CSI-2 v2.1, with 8-bit and 16-bit PPI data width and links with 1, 2, 4, or 8 data lanes
Provides up to 8 Independent Stream Output Interfaces, allowing a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, Data Type selection, and Virtual Channel or Data Type interleaving

Benefits

Full-Featured and Highly Configurable IP Core: Area customized for different applications
Integrates to Cadence or Third-Party MIPI D-PHY 2.1: Wide range of process nodes supported
Automotive Version Available: With safety manual and FMEDA

Block Diagram

Technical Specifications

Maturity

Silicon Proven

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