MIPI CSI-2 Controller Core

Overview

The MIPI CSI-2 controller core is optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management. For automotive safety-critical applications, an ASIL-B version of the core is available and includes a Safety Manual, Design Failure Mode & Effects Analysis (DFMEA) and Failure Mode, Effects and Diagnostic Analysis (FMEDA).

Key Features

Fully MIPI CSI-2 standard compliant
64 and 32-bit core widths
Transmit and Receive versions
Supports 1-8, 9.0+ Gbps D-PHY data lanes
Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
Supports all data types
Easy-to-use pixel-based interface
Optional AXI interface (Rx only)
Optional video interface
Delivered fully integrated and verified with target MIPI PHY
Complete FPGA-based demonstration system available
Optional ASIL-B Ready safety deliverables

Block Diagram

Deliverables

Core (source code)
Testbench (source code)
Complete documentation
Expert technical support
Maintenance updates

Technical Specifications

Foundry, Node

Any

Availability

Now

Request Info