CSI-2 transmitter controller for application processor
The Cadence® Transmitter (TX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is responsible for handling and encoding image sensor data (in multiple RGB, YUV, and RAW formats), as well as user-defined data formats, and converting these into CSI-2-compliant packets for transmission over a MIPI D-PHYSM link. The TX Controller IP for CSI-2 supports up to four independent pixel streams and can perform Virtual Channel and Data Type interleaving before transmission. Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the TX Controller IP for CSI-2 is engineered to quickly and easily integrate into any systemon-chip (SoC) design, and to connect seamlessly to a Cadence or third-party D-PHY via standard PHY-Protocol Interface (PPI). The TX Controller IP for CSI-2 is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP
MIPI CSI-2 TX Controller for v2.1
Overview
Key Features
- Compliant with MIPI CSI-2 v2.1 Specification
- Provides up to 4 independent stream input interfaces, with a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, and Data Type interleaving
- RTE – Efficient Packet Delimiter support (Option 1 and 2)
- Programmable Data Type and Word Count settings, with either 8 or 16 options selectable on a packet-bypacket basis
- Support for all primary and secondary data formats
- Support for MIPI D-PHY v2.1 specification, with 8-bit PPI data width and links with 1, 2, or 4 data lanes
- Optional extensions for loopback support on stream 0, for connection to Cadence Receiver Controller IP for CSI-2 (“RX Compatibility” mode
- 32-bit Arm® AMBA® APB Responder programming interface
- Support for external RAM/register or internal register-based stream buffer
- Supports ULPS on all data lanes and clock lane
Applications
- Automotive,
- Communications,
- Consumer Electronics,
- Data Processing,
- Industrial and Medical,
- Military/Civil Aerospace,
- Others
Deliverables
- Unencrypted, synthesizable Verilog HDL
- Cadence Genus™ Synthesis Solution scripts
- Documentation—Integration and User Guide, Release Notes
- Demonstration testbench with integrated Cadence Verification IP (VIP)
- Software Driver
Technical Specifications
Maturity
Silicon Proven