Adaptive Body Bias IP

• Integrated adaptive body bias (ABB) control loop
• Charge pumps for N-Well and P-Well voltages, operated from IO supply voltage level

• ABB generator, standard cells, SRAM
• Up to 9X performance
• 75% leakage reduction

• Single port SRAM compiler based on Racyics® R188 logic memory cell with dual-well architecture
• Supply voltage 0.55 V to 0.8 V enabled with Racyics® ABB

• Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
• Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB

• Integrated adaptive body bias control loop
• Charge pumps for N-Well and P-Well voltages, operated from IO supply voltage level, reverse bias capability
• Integrated PVT monitors
• True Independent regulation of NMOS and PMOS performance

Silicon proven 1-Port Register File SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.

• Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.

• Contains >300 cells, various Vt and channel length options
• Robust power supply rails on M2, optimized M1 pin access with at least two on-track M2 access points
• DFM and variability optimized layouts and variation aware placement attributes for automated place&route
• Enabled for reliable ULV operation down to 0.4 V in combination with adaptive forward body bias