ARM IP

• The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance.
• This system contains an 8 Master component, 16 Slave component AXI4 multi-matrix for supporting multiple high speed user AXI Master components while providing high performance with Cortex-A5 class processors.

• Fragment prepass.
• Doubled tiler throughput.
• Doubled shift-convert unit thoughput.
• Improved command stream frontend.
• Improved ray tracing performance.

• Supports all required features of CXL 3.1 and CXL 3.0
• Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
• Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications

• Supports all required features of CXL 3.1 and CXL 3.0
• Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
• Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications

• 32/64 Bit RISC-V core
• 5-stage pipeline
• In-order, Single issue
• Multicore Capable (up to 8 cores)

• Sustainable Innovation
• Scalable Performance
• Generative AI at the Edge
• System Level Solution

Arm Neoverse V3AE is the perfect platform for developing complex automated driving and ADAS vehicle systems.

• Fastest Path to Production Silicon
• World-Class Performance
• Leading-Edge Technology


 

• Fastest Path to Market for Neoverse N3
• Configurable for Cloud to Edge
• Highly Customizable

• 64-cores of Arm Neoverse V3
• 12-channels (40b) of DDR5/LPDDR5 memory
• 64-lanes of PCIe Gen5 or CXL I/O