AMBA AXI IP
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AMBA AXI - Validates AXI interface functionality, performance, and compliance
- The AMBA AXI Verification IP from XtremeSilica is a powerful tool designed to validate the functionality, performance, and protocol compliance of AXI interfaces in SoCs. It supports AXI3, AXI4, and AXI4-Lite protocols, ensuring efficient data transfers across systems.
- This versatile VIP is crucial in validating high-performance systems, enabling seamless communication between memory, processors, and peripherals. It is widely used in industries like AI, IoT, automotive, and high-speed computing for complex transaction scenarios
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AMBA AXI STREAM Verification IP
- Compliant with AMBA® AXI5- Stream and AXI4-Stream.
- Support for all types of AMBA AXI5-Stream and AXI4-STREAM components.
- Supports parameterized data widths.
- Supports byte stream transmission number of data and null bytes.
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Simulation VIP for AMBA AXI
- Multiple Agents
- Supports any number of agents
- Data and Address Widths
- All legal data and address widths
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AMBA AXI STREAM Verification IP
- Compliant with AMBA® AXI5- Stream and AXI4-Stream.
- Support for all types of AMBA AXI5-Stream and AXI4-STREAM components.
- Supports parameterized data widths.
- Supports byte stream transmission number of data and null bytes.
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AMBA AXI Target
- Completely Configurable registers and memories
- Configurable bus/address width
- Module has Asynchronous/Synchronous resets.
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AMBA AXI Data Prefetch Buffer
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable FIFO depth
- Programmable source address parameters
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AMBA AXI Data Writer Spreader
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable FIFO depth
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AMBA AXI Performance Monitor
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable number of AXI ports
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SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
- The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfers (both Full Duplex and Half Duplex) to/from a AMBA APB, AXI, or AHB Interconnect.
- The DB-SPI-S-AMBA-BRIDGE contains dual clock Transmit/Receive FIFOs and Finite State Machine control to process incoming SPI transmit/receive transactions, and a AMBA Master Interface (i.e. APB, AXI, AHB5) to read or write the SPI payload data with respect to the AMBA Interconnect. No processor is required for configuration or control; the DB-SPI-S-AMBA-BRIDGE operates autonomously from reset.
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PCI Express to AMBA 4 AXI/3 AXI Bridge
- Complete IP solution consists of digital controllers, PHYs and verification IP
- Fully supports the Synopsys Controller IP for PCI Express Endpoint, Root Port, Dual Mode (EP/RP), and Switch port types
- Fully compliant with the AMBA 3 AXI and 4 AXI interconnects
- Full protocol mapping from PCI Express to the AMBA 3 AXI or 4 AXI bus protocol