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AMBA AXI IP

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Compare 454 IP from 53 vendors (1 - 10)
  • CCIX 1.1 Controller with AMBA AXI interface
    • Controller IP for PCIe 5.0, 4.0, 3.1/3.0 Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations, with CCIX ESM Support and AMBA AXI Interconect User Interface
    Block Diagram -- CCIX 1.1 Controller with AMBA AXI interface
  • AMBA AXI Data Prefetch Buffer
    • Easy integraton
    • AMBA AXI 3.0 Compatible
    • Configurable FIFO depth
    • Programmable source address parameters
    Block Diagram -- AMBA AXI Data Prefetch Buffer
  • AMBA AXI Data Writer Spreader
    • Easy integraton
    • AMBA AXI 3.0 Compatible
    • Configurable FIFO depth
    Block Diagram -- AMBA AXI Data Writer Spreader
  • AMBA AXI Performance Monitor
    • Easy integraton
    • AMBA AXI 3.0 Compatible
    • Configurable number of AXI ports
    Block Diagram -- AMBA AXI Performance Monitor
  • AMBA AXI Target
    • Completely Configurable registers and memories
    • Configurable bus/address width
    • Module has Asynchronous/Synchronous resets.
  • PCIe 5.0 Controller with AMBA AXI interface
    • Compliant with the PCI Express 5.0 rev. 0.7 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8-, 16-, 32- and 64-bit) specifications
    Block Diagram -- PCIe 5.0 Controller with AMBA AXI interface
  • PCIe 4.0 Controller with AMBA AXI interface
    • Complies with the PCI Express Base 4.0 Specification,
    • Supports Endpoint and rootport configuration
    • Supports x16, x8, x4, x2, x1 at Gen4, Gen3, Gen2, Gen1 speeds
    Block Diagram -- PCIe 4.0 Controller with AMBA AXI interface
  • BitBLT Graphics Hardware Accelerator (AXI Bus)
    • Bit Block Transfer – 3 Independent Memory Sources of data:
    • 2D Raster Operations (ROP) performed on Block Transfers:
    • BitBLT Draw Features:
    • 2D Graphics Rendering Engine (Option):
    Block Diagram -- BitBLT Graphics Hardware Accelerator (AXI Bus)
  • AXI Bus Display Controller
    • Wide range of programmable Display Panel resolutions:
    • Releases supporting baseline display requirements and releases with following
    • optional display processing features:
    • Color Palette RAM per layer or single Palette for integrated display image
    Block Diagram -- AXI Bus Display Controller
  • AXI Bus Extender
    • Supports 64-bit and 128-bit AXIdata channels
    • Transparently bridges transactions, maintaining AXI ordering requirements
    • Makes use of Interlaken controller, a flexible and robust, chip-to-chip packet communication protocol controller
    • Maps AXI channels to independent Interlaken channels
    Block Diagram -- AXI Bus Extender
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Semiconductor IP