The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM in which the data may need to be available immediately. The prefetched data is stored in a FIFO. The parameters for the source addresses are configured by way of the APB bus.
AMBA AXI Data Prefetch Buffer
Overview
Key Features
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable FIFO depth
- Programmable source address parameters
- Automatic address calculation
- Output data FIFO with configurable depth
- Data input width 128-bit
- AXI input data width 128-bit
- APB interface for configuration and status
- Software reset
- Configurable AXI bursts
- Event Interrupt Indication
Benefits
- Low Gate Count
- Low Power Consumption
- Spyglass Lint Validated
- Standards Compliant
Block Diagram
Applications
- General System on Chip Use
Deliverables
- Synthesizable Verilog RTL
- Detailed block diagram and technical documents
Technical Specifications
Maturity
Fully Verified
Availability
Now
Related IPs
- AMBA AXI Data Writer Spreader
- PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- AMBA AXI Performance Monitor
- PCIe 4.0 Controller with AMBA AXI interface
- PCIe 5.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface