The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data may need to be spread into different address ranges. The data is input to a FIFO. The parameters for the destination addresses are configured by way of the APB bus. The destination address is calculated in two dimensions.
AMBA AXI Data Writer Spreader
Overview
Key Features
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable FIFO depth
- Programmable Destination address parameters
- 2 dimensional address calculation
- Input data FIFO with configurable depth
- Data input width 64-bit
- AXI write data width 64-bit
- APB interface for configuration and status
- Software reset
- Configurable AXI bursts
- Event Interrupt Indication
Benefits
- Low Gate Count
- Low Power Consumption
- Spyglass Lint Validated
- Standards Compliant
Block Diagram
Applications
- General System on Chip Use
Deliverables
- Synthesizable Verilog RTL
- Detailed block diagram and technical documents
Technical Specifications
Maturity
Fully Verified
Availability
Now
Related IPs
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- AMBA AXI Data Prefetch Buffer
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect