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10G Ethernet Switch IP

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Compare 20 IP from 13 vendors (1 - 10)
  • Ethernet Switch IP
    • Deterministic latency, 802.1Q-2022 CBS
  • 10G Unmanaged Ethernet Switch
    • No con figuration required
    • Full-crossbar matrix among ports implemented to allow maximum throughput
  • 100M/1G/2.5G/5G/10G Managed Ethernet Switch
    • Full-duplex 100M/1G/2.5G/5G/10G Ethernet Interfaces
    • Configurable from 3 up-to 32 Ethernet ports
  • 10G automotive Ethernet switch/TSN IP for advanced integrated architectures
    • Updated TSN feature set
    • Enhanced diagnostic
    • ASIL-B ISO26262
    • Configuration tools
  • Unmanaged Ethernet Switch IP Core
    • Automatic MAC address learning and aging
    • Support programmable static forwarding entries
    • Ethernet Multicast support
    • Full duplex Ethernet interfaces
    Block Diagram -- Unmanaged Ethernet Switch IP Core
  • 10G TSN Switch
    • Interfaces
    • Switching
    • Low Level Configuration
    • Time-Sensitive Networking
  • 1G/10G/25G Switching Ethernet Subsystem
    • Supports  1.25G or 10.3125G Ethernet
    • Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included
    • Detailed statistics gathering
    • Optional support for IEEE 1588 2-step hardware timestamping
  • 10G Ultra Low Latency Ethernet Solution
    • Ultra low latency MAC; Tx = 12.4ns , Rx = 15.5ns; (32-bit user interface mode)
    • Ultra low latency 10GBase-R PCS; Tx = 12.4ns, Rx = 12.4ns
    Block Diagram -- 10G Ultra Low Latency Ethernet Solution
  • 1G/10Gb Ethernet PHY Intel® FPGA IP
    • The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA)
    • The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard
    • The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.
    Block Diagram -- 1G/10Gb Ethernet PHY Intel® FPGA IP
  • 10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
    • Designed to 10-Gigabit Ethernet specification IEEE 802.3-2012 clause 49, Forward Error Correction (FEC) clause 74, and Auto-Negotiation clause 73
    • Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802.3-2012 clause 45
    • Available under the Xilinx Project Core License Agreement 
    • Supports LAN mode only 
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