10G Ultra Low Latency Ethernet Solution

Overview

Key Features

• Ultra low latency MAC; Tx = 12.4ns , Rx = 15.5ns; (32-bit user interface mode)
• Ultra low latency 10GBase-R PCS; Tx = 12.4ns, Rx = 12.4ns which can be directly connected to transceiver in PMA only mode
• Ultra low Round Trip Latency (MAC + PCS + Transceivers) of 62.7ns (Tx user interface In to Rx user interface Out, Latency numbers with Altera Stratix-V Transceiver)
• Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs
• Statistics counter block (for RMON and MIB)
• MDIO and I2C cores for external module and optical module status/control

Block Diagram

Deliverables

• Compiled synthesizable binaries (Netlists) for the MAC and PCS cores
• Technology specific transceiver wrappers for the selected device family
• Source code RTL (Verilog) for I2C, MDIO, RMON and Register-File blocks
• Self checking behavioral models and test benches for simulation
• Constraint files and synthesis scripts for design compilation
• A complete PCIe interface based reference design with: Top level wrapper (source files, Verilog) for user specific customizations
• Source files (Verilog) for the PICe application layer
• Binaries for the L2 packet generator and checker
• PCIe driver/API (source files, C) for Linux
• GUI application (Windows and Linux) for interfacing to the reference design
• Design guide(s) and user manuals Getting started Guide
• Core user guide
• reference design user guide
• USA based technical support by developers

Technical Specifications